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ISL8204M, ISL8206M
3.5
3.0
7
6
2.5
3.3V
5
3.3V
2.0
0.6V
1.5V
4
1.5V
0.6V
1.5
1.0
0.5
3
2
1
0.0
0
1
2
3
4
5
6
0
60
70
80
90
100
110
LOAD CURRENT (A)
FIGURE 26. POWER LOSS vs LOAD CURRENT (5V IN )
4.0
7
AMBIENT TEMPERATURE (°C)
FIGURE 27. DERATING CURVE (5V IN )
3.5
3.0
3.3V
5.0V
6
5
2.5
2.0
0.6V
1.5V
2.5V
4
5.0V
3.3V
2.5V
1.5
1.0
0.5
3
2
1
1.5V
0.6V
0.0
0
1
2
3
4
5
6
0
60
70
80
90
100
110
LOAD CURRENT (A)
FIGURE 28. POWER LOSS vs LOAD CURRENT (12V IN )
Thermal Considerations
Experimental power loss curves along with θ JA from thermal
modeling analysis can be used to evaluate the thermal
consideration for the module. The derating curves are derived
from the maximum power allowed while maintaining the
temperature below the maximum junction temperature of
+125°C. The power loss and derating curves apply for both
ISL8206M, and ISL8204M. The loss at 4A can be found by
tracing the power loss curve up at the load current of 4A. In
actual applications, other heat sources and design margins
should be considered.
Package Description
The structure of ISL8204M, ISL8206M belongs to the Quad Flat-
pack No-lead package (QFN). This kind of package has
advantages, such as good thermal and electrical conductivity, low
weight and small size. The QFN package is applicable for surface
mounting technology and is being more readily used in the
industry. The ISL8204M, ISL8206M contains several types of
devices, including resistors, capacitors, inductors and control ICs.
The ISL8204M, ISL8206M is a copper lead-frame based package
with exposed copper thermal pads, which have good electrical and
thermal conductivity. The copper lead frame and multi-component
assembly is overmolded with polymer mold compound to protect
these devices.
16
AMBIENT TEMPERATURE (°C)
FIGURE 29. DERATING CURVE (12V IN )
The package outline and typical PCB layout pattern design and
typical stencil pattern design are shown in the package outline
drawing L15.15x15 on page 20. The module has a small size of
15mmx15mmx3.5mm. Figure 25 shows typical reflow profile
parameters. These guidelines are general design rules. Users can
modify parameters according to their application.
PCB Layout Pattern Design
The bottom of ISL8204M, ISL8206M is a lead-frame footprint,
which is attached to the PCB using a surface mounting process.
The PCB layout pattern is shown in the Package Outline Drawing
L15.15x15 on page 20. The PCB layout pattern is essentially 1:1
with the QFN exposed pad and I/O termination dimensions,
except for the PCB lands being a slightly extended distance of
0.2mm (0.4mm max) longer than the QFN terminations, which
allows for solder filleting around the periphery of the package.
This ensures a more complete and inspectable solder joint. The
thermal lands on the PCB layout should match 1:1 with the
package exposed die pads.
FN6999.3
July 26, 2012
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